EXPANSIONS for PHASE RESEARCH:

- Runtime Phase Prediction and Phase-Driven Adaptations for multiple threads:
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- Need per thread virtual counters/ GPHT states - probably within PCB - would be much more portable if can be done with a LKM - Key challenge: tracking fixed instruction granularities, providing PMI interrupt for each thread simultaneously

- Runtime Phase Prediction and Phase-Driven Adaptations for multicoure/multichip:
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- very interesting issues, AMD Barcelona would be a good test bed for CMP - Woodcrest (DP-CMP2) for multichip. Each package can be configured separately but not each core - how can scheduling help in such a case for "phase aligining"? - we had already done simultaneous tracking with set_cpu_affinity, but haven't transferred to delta_instruction tracking

- Application Phase Classification methods Exploration (Power and Performance):
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Application -> sample -> Similarity criterion -> Dimension Transformation -> Clustering -> comparison

- Incorporating MDA in runtime phase clustering:
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- PCA is good for representation; MDA is good for discrimination. - Need to empriicially get the discriminant vectors - Or application defines them - Some kind of recurrence detection: -- transitions? -- lossy string matching? -- simple table? -- fuzzy clusters?

- Implementing the transition approach in HW with a management application
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--- HW reconf --- throttle --- CMP manage --- power gate

- Dynamically Tuning virtual memory: -----------------------------------------------------------------
- We had some initial attempt - Need more insight to Vmem, CS support - we can use our platform for power, etc

- More on Duration Prediction:
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- prediction tables and probabilistic approach - dynamic mgmt endgoal

- Regression/Estimation/Numerical Methods for Power/Thermal Estimation:
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- Back to power estimation with better validation support, - more detailed power estimations with counters. - Instead of top-down, try bottom-up with power values/thermal map - emphasis on estimators (multiple linear regressions, piecewise linear estimation, mutual info) - Alternatively: runtime, self updating model, like neural nets (ripples will be problem in such case) , so it updates wrt runtime power verification

- possible new approaches to phase detection; based on prior discussions:
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- shift/rotation invariant wavelet transform (wave-menu) - windowed xcorr - MDA, SVD, PCA, ICA, Registration, waveform matching - statistics (time series)/ mutual info - signal/image retrieval / feature extraction / humming recogn. - point matching - pattern recognition - lossy string matching - context free grammar (seiquitir) - runlength/markov chains - fuzzy clustering - How does general phase approach compare to odour matching problem? (compare to our neural network research)

- Leakage Mgmt/Power Gating Application with Phases:
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- Can we use phase info to guide application of where to power gate? - What are the break-even cycles? How does it relate to phase detection?

- BBVs and The effect of Sampling:
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- Power & IPC phases with BBVs. What if: - we sampled every PC? - we sampled every 10PC? - we sampled every 1000PC? What if? - we didn't hash? - hash to 1024? - hash to 512? - hash to 64? - hash to 8?

- Applying the BBV recurrence info + PMC phases to thermal mgmt:
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- Use our BBV and PWR with thermal modeling, with multiple contexts - Based on observed/predicted phases, do different context switch scenarios to better manage temperature. - Need to consider scheduling overheads/default nature of preemptive

NEW RESEARCH DIRECTIONS:

virtualization/scalable enterprise

many core/uncore/accelerators

three-tier approach
- expose parallelism/migrate - global power/perf/thermal - local actions

Embedded systems/MPSoC/ASIPs

BIG phase classifier/actioner for single core

Real-time systems/SLAs for GPHT based mgmt

variability(hetero+process)
- Variation and defect tolerance - self healing/fault tolerant threads/TM

security

ultra low power/ultra mobile/UMPC

disposable computing

biomedical/uarch

parallelism/data-prog/graphix-throughput processing convergence

QoS caches/cores

3D arch / embedded DRAM