-- -- File: Inst_decoder.vhd -- created by Design Wizard: 12/12/01 02:43:47 -- --{{ Section below this comment is automatically maintained -- and may be overwritten --{entity {Inst_decoder} architecture {Inst_decoder_bh}} library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.std_logic_arith.CONV_STD_LOGIC_VECTOR; entity Inst_decoder is generic (Tac : Time := 0 ns; tag : string := ""; origin_x, origin_y : real := 0.0); port ( IR_L : in STD_LOGIC_VECTOR (31 downto 0); IR_R : in STD_LOGIC_VECTOR (31 downto 0); ---------------------------------------------------------------------- Instr_type_L: out STD_LOGIC_VECTOR (8 downto 0); Instr_type_R: out STD_LOGIC_VECTOR (8 downto 0); ---------------------------------------------------------------------- Opcode_L : out STD_LOGIC_VECTOR (5 downto 0); Subopsw_L: out STD_LOGIC_VECTOR (7 downto 0); Rd_L : out STD_LOGIC_VECTOR (4 downto 0); Rs1_L : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L : out STD_LOGIC_VECTOR (4 downto 0); imm_L : out STD_LOGIC_VECTOR (63 downto 0); we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); -- pred file control signals wr_pred_addr1_L: out std_logic_vector (2 downto 0); wr_pred_addr2_L: out std_logic_vector (2 downto 0); we_pred_L : out STD_LOGIC_VECTOR (0 downto 0); pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L : out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L : out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L : out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L : out STD_LOGIC_VECTOR (4 downto 0); -- imm to PC for branch control needed to be added ---------------------------------------------------------------------- Opcode_R : out STD_LOGIC_VECTOR (5 downto 0); Subopsw_R: out STD_LOGIC_VECTOR (7 downto 0); Rd_R : out STD_LOGIC_VECTOR (4 downto 0); Rs1_R : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R : out STD_LOGIC_VECTOR (4 downto 0); imm_R : out STD_LOGIC_VECTOR (63 downto 0); we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); -- pred file control signals wr_pred_addr1_R: out std_logic_vector (2 downto 0); wr_pred_addr2_R: out std_logic_vector (2 downto 0); we_pred_R : out STD_LOGIC_VECTOR (0 downto 0); pred_R : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R : out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R : out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R : out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R : out STD_LOGIC_VECTOR (4 downto 0) -- imm to PC for branch control needed to be added ---------------------------------------------------------------------- ); end Inst_decoder; --}} End of automatically maintained section architecture Inst_decoder_bh of Inst_decoder is begin -- <> decode: process (IR_L, IR_R) variable tmp_pred : std_logic; variable ALU_inst_L,CMP_inst_L,CHPR_inst_L,JMP_inst_L,JMPreg_inst_L,MUL_inst_L,LD_inst_L,LDI_inst_L,ST_inst_L: integer; variable ALU_inst_R,CMP_inst_R,CHPR_inst_R,JMP_inst_R,JMPreg_inst_R,MUL_inst_R,LD_inst_R,LDI_inst_R,ST_inst_R: integer; variable Inst_format: integer; variable link,Rds : integer; -- link=0 means JMP_link, Rds=0 means R1 field is target Reg in format 1, -- otherwise it's Source Reg. variable OpL,OpR : std_logic_vector(5 downto 0); --variable : std_logic; begin pred_L <= IR_L(31 downto 29); pred_R <= IR_R(31 downto 29); OpL := IR_L(28 downto 23); Opcode_L <= OpL; OpR := IR_R(28 downto 23); Opcode_R <= OpR; case OpL is when "000000" => -- JMP format=0; Inst_format := 0; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=1;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; link := 0; when "000001" => -- JMP_link format=0; inst_format := 0; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=1;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; link := 1; Rds := 0; when "000010" => -- JMP_reg, format=1; inst_format := 1; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=1;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; link := 0; Rds := 1; when "000011" => -- JMP_reg_link, format=1; inst_format := 1; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=1;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; link := 1; Rds := 1; when "000100" => -- LDi_high, format=1; inst_format := 1; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=1;ST_inst_L:=0; link := 0; Rds := 0; when "000101" => -- LDi_low, format=1; inst_format := 1; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=1;ST_inst_L:=0; link := 0; Rds := 0; -- "000110" is not defined when "000111" => -- Trap inst_format := 0; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; link := 0; when "001000" => -- CMP, format= 7, i.e., 5a; inst_format := 7; ALU_inst_L:=0;CMP_inst_L:=1;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "001001" => -- CMPi, format= 8, i.e., 5b; inst_format := 8; ALU_inst_L:=0;CMP_inst_L:=1;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "001010" => -- Testbit, format= 8, i.e., 5b; inst_format := 8; ALU_inst_L:=0;CMP_inst_L:=1;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "001011" => -- Changepr, format=8, i.e., 5b; inst_format := 8; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=1;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "001100" => -- Changepr_ld, format=8, i.e., 5b; inst_format := 8; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=1;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; -- "001101" is undefined -- "001110" is undefined -- "001111" is undefined when "010000" => -- LD_1, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=1;LDI_inst_L:=0;ST_inst_L:=0; when "010001" => -- LD_2, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=1;LDI_inst_L:=0;ST_inst_L:=0; when "010010" => -- LD_4, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=1;LDI_inst_L:=0;ST_inst_L:=0; when "010011" => -- LD_8, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=1;LDI_inst_L:=0;ST_inst_L:=0; when "010100" => -- LD_1_upd, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=1;LDI_inst_L:=0;ST_inst_L:=0; when "010101" => -- LD_2_upd, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=1;LDI_inst_L:=0;ST_inst_L:=0; when "010110" => -- LD_4_upd, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=1;LDI_inst_L:=0;ST_inst_L:=0; when "010111" => -- LD_8_upd, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=1;LDI_inst_L:=0;ST_inst_L:=0; when "011000" => -- ST_1, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011001" => -- ST_2, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011010" => -- ST_4, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011011" => -- ST_8, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011100" => -- ST_1_upd, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011101" => -- ST_2_upd, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011110" => -- ST_4_upd, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011111" => -- ST_8_upd, format=2; inst_format := 2; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=1; when "100000" => -- ADDi, format=2; inst_format := 2; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "100001" => -- SUBi, format=2; inst_format := 2; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "100010" => -- ANDi, format=2; inst_format := 2; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "100011" => -- ORi, format=2; inst_format := 2; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "100100" => -- XORi, format=2; inst_format := 2; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "100101" => -- SLLi, format=2; inst_format := 2; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "100110" => -- SRAi, format=2; inst_format := 2; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "100111" => -- SRLi, format=2; inst_format := 2; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "101000" => -- Deposit, format=3; inst_format := 3; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "101001" => -- Extract, format=3; inst_format := 3; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "101010" => -- SHRP, format=6, i.e., 4c; inst_format := 6; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; -- "101011" is undefined -- "101100" is undefined -- "101101" is undefined -- "101111" is undefined when "110000" => -- PALU, format=4, i.e., 4a; inst_format := 4; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "110001" => -- PMUL_inst, format=4, i.e., 4a; inst_format := 4; ALU_inst_L:=0;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=1;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "110010" => -- PSSP_inst, format=4, i.e., 4a; inst_format := 4; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when "110011" => -- PSSPi_inst, format=5, i.e., 4b; inst_format := 5; ALU_inst_L:=1;CMP_inst_L:=0;CHPR_inst_L:=0;JMP_inst_L:=0;JMPreg_inst_L:=0;MUL_inst_L:=0;LD_inst_L:=0;LDI_inst_L:=0;ST_inst_L:=0; when others => assert (false) -- assert always report "Invalid ALU function!!" severity WARNING; end case; case inst_format is when 0 => Subopsw_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); if OpL="000001" then Rd_L <= "11111"; -- JMP_link target Reg is R31 else Rd_L <= "00000"; end if; -- Rd_L <= "00000"; -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_L(22 downto 0) <= IR_L(22 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); if IR_L(22)='0' then imm_L(63 downto 23)<= "00000000000000000000000000000000000000000"; else imm_L(63 downto 23)<= "11111111111111111111111111111111111111111"; end if; --imm_L <= STD_LOGIC_VECTOR(signed(IR_L(22 downto 0))); -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); if OpL="000001" then we_RF_L <= "1"; else we_RF_L <= "0"; end if; -- pred file control signals wr_pred_addr1_L <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= "000"; --: out std_logic_vector (2 downto 0); we_pred_L <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 1 => Subopsw_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); if OpL="000011" then Rd_L <= "11111"; else if OpL="000100" or OpL="000101" then Rd_L <= IR_L(22 downto 18); else Rd_L <= "00000"; end if; end if; -- Rd_L <= "00000"; -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); if OpL="000010" or OpL="000011" then Rs1_L <= IR_L(22 downto 18); else Rs1_L <= "00000"; end if; --Rs1_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); if OpL="000010" or OpL="000011" then imm_L <= x"0000000000000000"; else imm_L(17 downto 0) <= IR_L(17 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); if iR_L(17)='0' then imm_L(63 downto 18)<= "0000000000000000000000000000000000000000000000"; else imm_L(63 downto 18)<= "1111111111111111111111111111111111111111111111"; end if; --imm_L <= STD_LOGIC_VECTOR(signed(IR_L(17 downto 0))); end if; --imm_L(22 downto 0) <= IR_L(22 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); --imm_L(63 downto 23)<= "00000000000000000000000000000000000000000"; -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); if OpL="000010" then we_RF_L <= "0"; else we_RF_L <= "1"; end if; -- pred file control signals wr_pred_addr1_L <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= "000"; --: out std_logic_vector (2 downto 0); we_pred_L <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 2 => Subopsw_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); if OpL="010100" or OpL="010101" or OpL="010110" or OpL="010111" or OpL="011100" or OpL="011101" or OpL="011110" or OpL="011111" then Rd_L <= IR_L(22 downto 18); -- : out STD_LOGIC_VECTOR (4 downto 0); else if OpL="010000" or OpL="010001" or OpL="010010" or OpL="010011" or OpL="011000" or OpL="011001" or OpL="011010" or OpL="011011" then Rd_L <= "00000"; else Rd_L <= IR_L(17 downto 13); end if; end if; Rs1_L <= IR_L(22 downto 18); -- : out STD_LOGIC_VECTOR (4 downto 0); if OpL="011000" or OpL="011001" or OpL="011010" or OpL="011011" or OpL="011100" or OpL="011101" or OpL="011110" or OpL="011111" then Rs2_L <= IR_L(17 downto 13); -- : out STD_LOGIC_VECTOR (4 downto 0); else Rs2_L <= "00000"; end if; -- Rs2_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_L(12 downto 0) <= IR_L(12 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); imm_L(63 downto 13)<= "000000000000000000000000000000000000000000000000000"; -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); if OpL="010100" or OpL="010101" or OpL="010110" or OpL="010111" or OpL="011100" or OpL="011101" or OpL="011110" or OpL="011111" then we_RF_L <= "1"; else we_RF_L <= "0"; end if; -- pred file control signals wr_pred_addr1_L <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= "000"; --: out std_logic_vector (2 downto 0); we_pred_L <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- if OpL="011000" or OpL="011001" or OpL="011010" or OpL="011011" or OpL="011100" or OpL="011101" or OpL="011110" or OpL="011111" then we_Dcache_L <= "1"; -- : out STD_LOGIC_VECTOR (4 downto 0); else we_Dcache_L <= "0"; end if; -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); if OpL="010000" or OpL="010001" or OpL="010010" or OpL="010011" or OpL="010100" or OpL="010101" or OpL="010110" or OpL="010111" then we_RF_M_L <= "1"; --: out STD_LOGIC_VECTOR (0 downto 0); Rd_M_L <= IR_L(17 downto 13); else we_RF_M_L <= "0"; Rd_M_L <= "00000"; end if; -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0) when 3 => Subopsw_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); Rd_L <= IR_L(17 downto 13); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_L <= IR_L(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_L(12 downto 0) <= IR_L(12 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); imm_L(63 downto 13)<= "000000000000000000000000000000000000000000000000000"; -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); we_RF_L <= "1"; -- pred file control signals wr_pred_addr1_L <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= "000"; --: out std_logic_vector (2 downto 0); we_pred_L <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 4 => -- format 4a Subopsw_L <= IR_L(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_L <= IR_L(12 downto 8); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_L <= IR_L(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L <= IR_L(17 downto 13); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_L <= x"0000000000000000"; --: out STD_LOGIC_VECTOR (63 downto 0); -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); we_RF_L <= "1"; -- pred file control signals wr_pred_addr1_L <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= "000"; --: out std_logic_vector (2 downto 0); we_pred_L <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 5 => -- format 4b Subopsw_L <= IR_L(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_L <= IR_L(17 downto 13); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_L <= IR_L(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_L(4 downto 0) <= IR_L(12 downto 8); --: out STD_LOGIC_VECTOR (63 downto 0); imm_L(63 downto 5) <= "00000000000000000000000000000000000000000000000000000000000"; -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); we_RF_L <= "1"; -- pred file control signals wr_pred_addr1_L <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= "000"; --: out std_logic_vector (2 downto 0); we_pred_L <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 6 => -- format 4c Subopsw_L <= IR_L(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_L <= IR_L(12 downto 8); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_L <= IR_L(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L <= IR_L(17 downto 13); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_L(7 downto 0) <= IR_L(7 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); imm_L(63 downto 8) <= x"00000000000000"; -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); we_RF_L <= "1"; -- pred file control signals wr_pred_addr1_L <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= "000"; --: out std_logic_vector (2 downto 0); we_pred_L <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= IR_L(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 7 => -- format 5a Subopsw_L <= IR_L(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_L <= "00000"; -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_L <= IR_L(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L <= IR_L(17 downto 13); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); -- imm_L <= x"0000000000000000"; --: out STD_LOGIC_VECTOR (63 downto 0); imm_L(3 downto 0) <= IR_L(3 downto 0); imm_L(63 downto 4) <=x"000000000000000"; -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); we_RF_L <= "0"; -- pred file control signals wr_pred_addr1_L <= IR_L(9 downto 7); --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= IR_L(6 downto 4); --: out std_logic_vector (2 downto 0); we_pred_L <= "1"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= IR_L(3 downto 0); --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= x"00"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 8 => -- format 5b Subopsw_L <= IR_L(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_L <= IR_L(22 downto 18); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_L <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); -- imm_L <= x"0000000000000000"; --: out STD_LOGIC_VECTOR (63 downto 0); -- imm_L(3 downto 0) <= IR_L(3 downto 0); -- imm_L(17 downto 10) <= IR_L(17 downto 10); -- imm_L(63 downto 18) <= "0000000000000000000000000000000000000000000000"; -- imm_L(9 downto 4) <= "000000"; imm_L(7 downto 0) <= IR_L(17 downto 10); imm_L(63 downto 8) <=x"00000000000000"; -- we_RF_L: out STD_LOGIC_VECTOR (0 downto 0); if OpL = "001010" then -- Testbit we_RF_L <= "1"; else we_RF_L <= "0"; end if; -- pred file control signals wr_pred_addr1_L <= IR_L(9 downto 7); --: out std_logic_vector (2 downto 0); wr_pred_addr2_L <= IR_L(6 downto 4); --: out std_logic_vector (2 downto 0); if OpL = "001010" then -- Testbit we_pred_L <= "0"; else we_pred_L <= "1"; -- : out STD_LOGIC_VECTOR (0 downto 0); end if; -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_L <= IR_L(3 downto 0); --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_L <= IR_L(17 downto 10); --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_L <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_L <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when others => assert (false) -- assert always report "Invalid instruction format!!!" severity WARNING; end case; case OpR is when "000000" => -- JMP format=0; Inst_format := 0; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=1;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; link := 0; when "000001" => -- JMP_link format=0; inst_format := 0; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=1;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; link := 1; Rds := 0; when "000010" => -- JMP_reg, format=1; inst_format := 1; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=1;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; link := 0; Rds := 1; when "000011" => -- JMP_reg_link, format=1; inst_format := 1; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=1;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; link := 1; Rds := 1; when "000100" => -- LDi_high, format=1; inst_format := 1; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=1;ST_inst_L:=0; link := 0; Rds := 0; when "000101" => -- LDi_low, format=1; inst_format := 1; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=1;ST_inst_L:=0; link := 0; Rds := 0; -- "000110" is not defined when "000111" => -- Trap inst_format := 0; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; link := 0; when "001000" => -- CMP, format= 7, i.e., 5a; inst_format := 7; ALU_inst_R:=0;CMP_inst_R:=1;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "001001" => -- CMPi, format= 8, i.e., 5b; inst_format := 8; ALU_inst_R:=0;CMP_inst_R:=1;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "001010" => -- Testbit, format= 8, i.e., 5b; inst_format := 8; ALU_inst_R:=0;CMP_inst_R:=1;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "001011" => -- Changepr, format=8, i.e., 5b; inst_format := 8; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=1;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "001100" => -- Changepr_ld, format=8, i.e., 5b; inst_format := 8; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=1;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; -- "001101" is undefined -- "001110" is undefined -- "001111" is undefined when "010000" => -- LD_1, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=1;LDI_inst_R:=0;ST_inst_R:=0; when "010001" => -- LD_2, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=1;LDI_inst_R:=0;ST_inst_R:=0; when "010010" => -- LD_4, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=1;LDI_inst_R:=0;ST_inst_R:=0; when "010011" => -- LD_8, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=1;LDI_inst_R:=0;ST_inst_R:=0; when "010100" => -- LD_1_upd, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=1;LDI_inst_R:=0;ST_inst_R:=0; when "010101" => -- LD_2_upd, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=1;LDI_inst_R:=0;ST_inst_R:=0; when "010110" => -- LD_4_upd, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=1;LDI_inst_R:=0;ST_inst_R:=0; when "010111" => -- LD_8_upd, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=1;LDI_inst_R:=0;ST_inst_R:=0; when "011000" => -- ST_1, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011001" => -- ST_2, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011010" => -- ST_4, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011011" => -- ST_8, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011100" => -- ST_1_upd, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011101" => -- ST_2_upd, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011110" => -- ST_4_upd, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=0;ST_inst_L:=1; when "011111" => -- ST_8_upd, format=2; inst_format := 2; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_L:=0;ST_inst_L:=1; when "100000" => -- ADDi, format=2; inst_format := 2; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "100001" => -- SUBi, format=2; inst_format := 2; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "100010" => -- ANDi, format=2; inst_format := 2; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "100011" => -- ORi, format=2; inst_format := 2; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "100100" => -- XORi, format=2; inst_format := 2; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "100101" => -- SLLi, format=2; inst_format := 2; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "100110" => -- SRAi, format=2; inst_format := 2; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "100111" => -- SRLi, format=2; inst_format := 2; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "101000" => -- Deposit, format=3; inst_format := 3; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "101001" => -- Extract, format=3; inst_format := 3; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "101010" => -- SHRP, format=6, i.e., 4c; inst_format := 6; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; -- "101011" is undefined -- "101100" is undefined -- "101101" is undefined -- "101111" is undefined when "110000" => -- PALU, format=4, i.e., 4a; inst_format := 4; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "110001" => -- PMUL_inst, format=4, i.e., 4a; inst_format := 4; ALU_inst_R:=0;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=1;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "110010" => -- PSSP_inst, format=4, i.e., 4a; inst_format := 4; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when "110011" => -- PSSPi_inst, format=5, i.e., 4b; inst_format := 5; ALU_inst_R:=1;CMP_inst_R:=0;CHPR_inst_R:=0;JMP_inst_R:=0;JMPreg_inst_R:=0;MUL_inst_R:=0;LD_inst_R:=0;LDI_inst_R:=0;ST_inst_R:=0; when others => assert (false) -- assert always report "Invalid ALU function!!" severity WARNING; end case; case inst_format is when 0 => Subopsw_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); if OpR="000001" then Rd_R <= "11111"; -- JMP_link target Reg is R31 else Rd_R <= "00000"; end if; -- Rd_R <= "00000"; -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_R(22 downto 0) <= IR_R(22 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); if IR_R(22)='0' then imm_R(63 downto 23)<= "00000000000000000000000000000000000000000"; else imm_R(63 downto 23)<= "11111111111111111111111111111111111111111"; end if; --imm_R(63 downto 23)<= "00000000000000000000000000000000000000000"; --imm_R <= STD_LOGIC_VECTOR(signed(IR_R(22 downto 0))); -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); if OpR="000001" then we_RF_R <= "1"; else we_RF_R <= "0"; end if; -- pred file control signals wr_pred_addr1_R <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= "000"; --: out std_logic_vector (2 downto 0); we_pred_R <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 1 => Subopsw_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); if OpR="000011" then Rd_R <= "11111"; else if OpR="000100" or OpR="000101" then Rd_R <= IR_R(22 downto 18); else Rd_R <= "00000"; end if; end if; -- Rd_R <= "00000"; -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); if OpR="000010" or OpR="000011" then Rs1_R <= IR_R(22 downto 18); else Rs1_R <= "00000"; end if; --Rs1_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); if OpR="000010" or OpR="000011" then imm_R <= x"0000000000000000"; else imm_R(17 downto 0) <= IR_R(17 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); if IR_R(17)='0' then imm_R(63 downto 18)<= "0000000000000000000000000000000000000000000000"; else imm_R(63 downto 18)<= "1111111111111111111111111111111111111111111111"; end if; --imm_R(63 downto 18)<= "0000000000000000000000000000000000000000000000"; --imm_R <= STD_LOGIC_VECTOR(signed(IR_R(17 downto 0))); end if; --imm_R(22 downto 0) <= IR_R(22 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); --imm_R(63 downto 23)<= "00000000000000000000000000000000000000000"; -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); if OpR="000010" then we_RF_R <= "0"; else we_RF_R <= "1"; end if; -- pred file control signals wr_pred_addr1_R <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= "000"; --: out std_logic_vector (2 downto 0); we_pred_R <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 2 => Subopsw_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); if OpR="010100" or OpR="010101" or OpR="010110" or OpR="010111" or OpR="011100" or OpR="011101" or OpR="011110" or OpR="011111" then Rd_R <= IR_R(22 downto 18); -- : out STD_LOGIC_VECTOR (4 downto 0); else if OpR="010000" or OpR="010001" or OpR="010010" or OpR="010011" or OpR="011000" or OpR="011001" or OpR="011010" or OpR="011011" then Rd_R <= "00000"; else Rd_R <= IR_R(17 downto 13); end if; end if; Rs1_R <= IR_R(22 downto 18); -- : out STD_LOGIC_VECTOR (4 downto 0); if OpR="011000" or OpR="011001" or OpR="011010" or OpR="011011" or OpR="011100" or OpR="011101" or OpR="011110" or OpR="011111" then Rs2_R <= IR_R(17 downto 13); -- : out STD_LOGIC_VECTOR (4 downto 0); else Rs2_R <= "00000"; end if; -- Rs2_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_R(12 downto 0) <= IR_R(12 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); imm_R(63 downto 13)<= "000000000000000000000000000000000000000000000000000"; -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); if OpR="010100" or OpR="010101" or OpR="010110" or OpR="010111" then we_RF_R <= "0"; else we_RF_R <= "1"; end if; -- pred file control signals wr_pred_addr1_R <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= "000"; --: out std_logic_vector (2 downto 0); we_pred_R <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- if OpR="011000" or OpR="011001" or OpR="011010" or OpR="011011" or OpR="011100" or OpR="011101" or OpR="011110" or OpR="011111" then we_Dcache_R <= "1"; -- : out STD_LOGIC_VECTOR (4 downto 0); else we_Dcache_R <= "0"; end if; -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); if OpR="010000" or OpR="010001" or OpR="010010" or OpR="010011" or OpR="010100" or OpR="010101" or OpR="010110" or OpR="010111" then we_RF_M_R <= "1"; --: out STD_LOGIC_VECTOR (0 downto 0); Rd_M_R <= IR_R(17 downto 13); else we_RF_M_R <= "0"; Rd_M_R <= "00000"; end if; -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0) when 3 => Subopsw_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); Rd_R <= IR_R(17 downto 13); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_R <= IR_R(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_R(12 downto 0) <= IR_R(12 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); imm_R(63 downto 13)<= "000000000000000000000000000000000000000000000000000"; -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); we_RF_R <= "1"; -- pred file control signals wr_pred_addr1_R <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= "000"; --: out std_logic_vector (2 downto 0); we_pred_R <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 4 => -- format 4a Subopsw_R <= IR_R(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_R <= IR_R(12 downto 8); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_R <= IR_R(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R <= IR_R(17 downto 13); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_R <= x"0000000000000000"; --: out STD_LOGIC_VECTOR (63 downto 0); -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); we_RF_R <= "1"; -- pred file control signals wr_pred_addr1_R <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= "000"; --: out std_logic_vector (2 downto 0); we_pred_R <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 5 => -- format 4b Subopsw_R <= IR_R(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_R <= IR_R(17 downto 13); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_R <= IR_R(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_R(4 downto 0) <= IR_R(12 downto 8); --: out STD_LOGIC_VECTOR (63 downto 0); imm_R(63 downto 5) <= "00000000000000000000000000000000000000000000000000000000000"; -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); we_RF_R <= "1"; -- pred file control signals wr_pred_addr1_R <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= "000"; --: out std_logic_vector (2 downto 0); we_pred_R <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= "00000000"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 6 => -- format 4c Subopsw_R <= IR_R(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_R <= IR_R(12 downto 8); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_R <= IR_R(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R <= IR_R(17 downto 13); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); imm_R(7 downto 0) <= IR_R(7 downto 0); --: out STD_LOGIC_VECTOR (63 downto 0); imm_R(63 downto 8) <= x"00000000000000"; -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); we_RF_R <= "1"; -- pred file control signals wr_pred_addr1_R <= "000"; --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= "000"; --: out std_logic_vector (2 downto 0); we_pred_R <= "0"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= "0000"; --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= IR_R(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 7 => -- format 5a Subopsw_R <= IR_R(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_R <= "00000"; -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_R <= IR_R(22 downto 18); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R <= IR_R(17 downto 13); -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); --imm_R <= x"0000000000000000"; --: out STD_LOGIC_VECTOR (63 downto 0); imm_R(3 downto 0) <= IR_R(3 downto 0); imm_R(63 downto 4) <=x"000000000000000"; -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); we_RF_R <= "0"; -- pred file control signals wr_pred_addr1_R <= IR_R(9 downto 7); --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= IR_R(6 downto 4); --: out std_logic_vector (2 downto 0); we_pred_R <= "1"; -- : out STD_LOGIC_VECTOR (0 downto 0); -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= IR_R(3 downto 0); --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= x"00"; --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when 8 => -- format 5b Subopsw_R <= IR_R(7 downto 0); --: out STD_LOGIC_VECTOR (7 downto 0); Rd_R <= IR_R(22 downto 18); -- no target Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs1_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); Rs2_R <= "00000"; -- no source Reg actually : out STD_LOGIC_VECTOR (4 downto 0); --imm_R <= x"0000000000000000"; --: out STD_LOGIC_VECTOR (63 downto 0); -- imm_R(3 downto 0) <= IR_R(3 downto 0); -- imm_R(17 downto 10) <= IR_R(17 downto 10); -- imm_R(63 downto 18) <= "0000000000000000000000000000000000000000000000"; -- imm_R(9 downto 4) <= "000000"; imm_R(7 downto 0) <= IR_R(17 downto 10); imm_R(63 downto 8) <=x"00000000000000"; -- we_RF_R: out STD_LOGIC_VECTOR (0 downto 0); if OpR = "001010" then -- Testbit we_RF_R <= "1"; else we_RF_R <= "0"; end if; -- pred file control signals wr_pred_addr1_R <= IR_R(9 downto 7); --: out std_logic_vector (2 downto 0); wr_pred_addr2_R <= IR_R(6 downto 4); --: out std_logic_vector (2 downto 0); if OpR = "001010" then -- Testbit we_pred_R <= "0"; else we_pred_R <= "1"; -- : out STD_LOGIC_VECTOR (0 downto 0); end if; -- pred_L : out STD_LOGIC_VECTOR (2 downto 0); pred_imm4_R <= IR_R(3 downto 0); --: out STD_LOGIC_VECTOR (3 downto 0); pred_imm8_R <= IR_R(17 downto 10); --: out STD_LOGIC_VECTOR (7 downto 0); -- we_Dcache_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); we_RF_M_R <= "0"; --: out STD_LOGIC_VECTOR (0 downto 0); -- Rd_M_R <= "00000"; --: out STD_LOGIC_VECTOR (4 downto 0); when others => assert (false) -- assert always report "Invalid instruction format!!!" severity WARNING; end case; Instr_type_L(8 downto 8) <= CONV_STD_LOGIC_VECTOR(ALU_inst_L,1); Instr_type_L(7 downto 7) <= CONV_STD_LOGIC_VECTOR(CMP_inst_L,1); Instr_type_L(6 downto 6) <= CONV_STD_LOGIC_VECTOR(CHPR_inst_L,1); Instr_type_L(5 downto 5) <= CONV_STD_LOGIC_VECTOR(JMP_inst_L,1); Instr_type_L(4 downto 4) <= CONV_STD_LOGIC_VECTOR(JMPreg_inst_L,1); Instr_type_L(3 downto 3) <= CONV_STD_LOGIC_VECTOR(MUL_inst_L,1); Instr_type_L(2 downto 2) <= CONV_STD_LOGIC_VECTOR(LD_inst_L,1); Instr_type_L(1 downto 1) <= CONV_STD_LOGIC_VECTOR(LDI_inst_L,1); Instr_type_L(0 downto 0) <= CONV_STD_LOGIC_VECTOR(ST_inst_L,1); Instr_type_R(8 downto 8) <= CONV_STD_LOGIC_VECTOR(ALU_inst_R,1); Instr_type_R(7 downto 7) <= CONV_STD_LOGIC_VECTOR(CMP_inst_R,1); Instr_type_R(6 downto 6) <= CONV_STD_LOGIC_VECTOR(CHPR_inst_R,1); Instr_type_R(5 downto 5) <= CONV_STD_LOGIC_VECTOR(JMP_inst_R,1); Instr_type_R(4 downto 4) <= CONV_STD_LOGIC_VECTOR(JMPreg_inst_R,1); Instr_type_R(3 downto 3) <= CONV_STD_LOGIC_VECTOR(MUL_inst_R,1); Instr_type_R(2 downto 2) <= CONV_STD_LOGIC_VECTOR(LD_inst_R,1); Instr_type_R(1 downto 1) <= CONV_STD_LOGIC_VECTOR(LDI_inst_R,1); Instr_type_R(0 downto 0) <= CONV_STD_LOGIC_VECTOR(ST_inst_R,1); end process decode; end Inst_decoder_bh;