-- -- File: Dcaceh_tmp.vhd -- created by Design Wizard: 01/14/02 05:54:46 -- --{{ Section below this comment is automatically maintained -- and may be overwritten --{entity {Dcaceh_tmp} architecture {Dcaceh_tmp_bh}} library IEEE; use IEEE.std_logic_1164.all; --use IEEE.numeric_std.to_integer; use IEEE.std_logic_arith.all; entity Dcaceh_tmp is port ( Raddr: in STD_LOGIC_VECTOR (31 downto 0); Waddr: in STD_LOGIC_VECTOR (31 downto 0); we: in STD_LOGIC; Wdata: in STD_LOGIC_VECTOR (63 downto 0); Dcacheout: out STD_LOGIC_VECTOR (63 downto 0) ); end Dcaceh_tmp; --}} End of automatically maintained section architecture Dcaceh_tmp_bh of Dcaceh_tmp is type cache is array(0 to (1024/4-1)) of std_logic_vector(63 downto 0); signal Dcache : cache; begin process (Raddr, Waddr, Wdata, we) variable dmem_ini: boolean := TRUE; variable i : integer := 0; variable dmem : cache; variable addr : integer; begin if (dmem_ini) then i := 0; while (i < (1024/4)) loop --dmem(i) := x"0000000000000000"; dmem(i) := CONV_STD_LOGIC_VECTOR(i*256,64); i := i+1; end loop; dmem_ini := FALSE; end if; -- do write first if enabled if we='1' then -- write enable is true addr := conv_integer(unsigned(Waddr(31 downto 3))); dmem(addr) := Wdata; end if; --do read addr := conv_integer(unsigned(Raddr(31 downto 3))); Dcacheout <= dmem(addr); --update signal Dcache Dcache <= dmem; end process; end Dcaceh_tmp_bh;